There has been an increased demand for active safety systems for vehicles. Active safety systems require multiple radar sensors per vehicle, each radar sensor typically working with a specific radar technology. In an automotive application, the radar sensors are mostly built using a number of integrated circuits (ICs), sometimes referred to as ‘chips’. The current trend is towards offering a radar system on chip (SoC), using a radio frequency (RF) complementary metal-oxide-semiconductor (CMOS) process technology) solution in order to reduce cost and power consumption.
Frequency-modulated continuous wave (FMCW) radar sensors transmit frequency modulated signals, and radar receivers substantially simultaneously receive their echo. The received echo is then mixed with the transmitted signal and results in a low frequency signal having a frequency of:
                    Fb        =                                            2              ×              Range                        c                    ×                                    Modulation              ⁢                                                          ⁢              BW                                      Ramp              ⁢                                                          ⁢              duration                                                          [        1        ]            at the output of the mixer, the so-called beat frequency (Fb). By analysing the beat frequency, the range parameter (i.e. a distance to targets) can be extracted.
Commercial automotive radar sensors typically include multiple receivers and transmitters (the combination of which is referred to as transceivers (TRx)). A microcontroller (MCU) performs digital control of the transceiver circuits and digital signal processing of the digitized data (e.g. fast fourier transform (FFT) and digital signal processing) in order to output processed radar data to the MCU of the vehicle.
Next generation high performance radar solutions used for highly automated or fully autonomous driving will need to comply with stringent radar angular resolution requirements in both azimuth and elevation. Angular resolution is directly related to the radar system number of receiver antennas and their location with respect to each other. Current monolithic radar transceiver ICs are typically constrained to contain only a few transceiver channels, as the complexity and cost and heat dissipation problems of integrating more transceiver channels on the same chip increases substantially with the number of ICs that are included.
To allow increased angular resolution in both azimuth and elevation, a multi-chip set solution with a master device and several slaves may be used, as illustrated in FIG. 1. In this illustration, a known radar unit cascades two radar TRx chips. One of the radar TRx chips is defined as the master device 110, which contains a first set of transmitter circuits coupled to transmit antennas 112 and a first set of receiver circuits coupled to receive antennas 114. The master device 110 (or IC) provides a number of signals 130 to one or more slave device(s) 120. In this way, master and several slaves are cascaded coherently to increase the number of transmit and receive channels, thereby enabling an increase in sensor accuracy to improve angle resolution.
Each master device 110 and slave device 120 embeds several receiver and transmitter channels, and a microcontroller unit (MCU) is used to combine all received data from all receivers, as well as to control and program the master device 110 and slaves devices 120. The master device 110 is arranged to distribute the Local Oscillator (LO) signal 140 off-chip through transmission lines on the printed circuit board (PCB) 100 to other radar chips (in this case the one other TRx chip functioning as a slave device 120). The LO signal 140 is used for the different transmitters and receivers, and is typically star-routed (i.e. routed via equal length paths) to each device to guarantee the same delay and exact phase coherence between all devices (which are sometimes separate ICs). The slave device 120 (and further slave device(s) 123) contains a second set of transmitter circuits coupled to transmit antennas 122 and a second set of receiver circuits coupled to receive antennas 124.
The distribution of the LO signal 140 from the master device 110 ensures that the slave device 120 is also able to use the LO signal 140, and thereby ensure that the transmitting signal frequency and the clock frequency of the down mixer of different radar TRx are the same. The LO signal 140 is used by all devices (including the master device 110 wherein the LO signal 140 is routed out of the master device 110 and thereafter back into the master device 110. Typically, in master-slave arrangements, the LO signal 140 is routed with symmetrical PCB lengths in order to ensure that all receivers (encompassing a respective down mixer) in each master device 110 and slave device(s) 120, 123 of the system receive the same LO with same phase. Phase coherence is mandatory for cascaded systems. Other control signals may be synchronized with a lower speed clock, for example an analog-to-digital converter (ADC) clock, which may be used across multiple ICs/devices.
The master device 110 is coupled to the MCU 160, which includes various interfaces, such as a serial-parallel interface (SPI) 162, a general purpose data input-output port 170, a ramp frame start (RFS) circuit 168, as well as a MCU clock interface 164, this clock signal 165 generally provided by the master device 110.
The RFS signal can be either (i) generated and distributed by the MCU 160, through a dedicated pin on both the MCU 160 (RFS_out) and a single pin on master device(s) 110 and slave device(s) 120, 123 (RFS_in) or (ii) generated and distributed by the master device 110, where there is no pin needed for MCU 160 in this case.
In the first known architecture (i), as illustrated in FIG. 1 and which is the predominant architecture used in most current master-slave arrangements, RFS circuit 168 generates a RFS signal 166 that is used to trigger a starting point of modulation timing engines within each master device and slave device. The RFS signal 166 is generated by the MCU 160 and requires at least one dedicated MCU pin. The RFS can also be generated by the master device 110, through a SPI command from MCU 160 via RFS signal 140. In this case, generally two pins are needed in the master device 110 (to support RFSout, RFSin) and one pin in each slave device (RFSin) in order to allow a star distribution that is preferred to ensure a good symmetry of RFS signal. However, even using star connected PCB routing in the first architecture (i), perfect time alignment of frame start inside master device(s) 110 and slave devices 120, 123 is not possible because the MCU 160 and master device(s) 110 and slave devices 120, 123 are not synchronized, e.g. they are subject to different pad delays, no control on timing generation of RFS from MCU time engine, etc.
In the second known architecture (ii), when the RFS is generated from the master device 110: the signal to start the generation of RFS comes from a SPI command from the MCU 160. Thus, no RFS at the MCU side is needed in this case. The RFS is then generated by the master device 110. The connection from master device 110 to slave devices 120, 123 for routing that RFS signal can be performed in two different ways:                (a) a not star connected manner using a single pin on each master device 110 and slave device(s) 120, 123, so no alignment is possible: and        (b) in a star connected manner whereby two pins (RFS_out and RFS_in) are used in the master device 110, and a single pin (RFS_in) used in each in slave device(s) 120, 123. This star routing ensures the symmetry of the RFS signal length in all chips, and thereby achieves a good alignment of chirp start signal (frame start). However, the inventors have recognised that this alignment is not sufficient to ensure the ADC clocks (i.e. the M/S clocks on each master device 110 and slave device(s) 120, 123) and RFS signal are synchronized between each other.        
A master-slave (MS) clock signal 142 is generated by the master device and used as a time base for synchronization of the microcontroller time based events with any other master device and all slave devices 123. The connection to the MCU 160 consists of SPI control lines 163 and digital data line signals from all the ICs back to the MCU 160 for later signal processing, in a given data format (e.g. Mobile Industry Processor Interface Camera Serial Interface (MIPI CSI-2), low voltage differential signalling (LVDS) or other formats).
The cascading master-slave (MS) clock signals (MS_clkP, MS_clkN) 142 are specifically used for time based synchronization of the sampling moments on the ADCs of several master and slave devices.
For optimal operation of distributed radar systems, it is important that these signals (LO 140, MS clock signal 142 and RFS signal 166) are synchronous across all receiver circuits on different devices. This means that, after calibration of the phase difference between all receiver channels in all master and slave devices, the voltage supply Vcc, temperature and aging variation between all devices distributed in the PCB should not change the initial clock alignment, for example after a one-time calibration operation is performed at radar module level.
A primary problem with such cascaded systems is clock distribution and synchronization. Problems arise due to any misalignment between clock valid and frame start timings between master device and slave device(s), due to different printed circuit board (PCB) delays between components, devices, circuits. This problem is typically overcome by adopting a MS clock distribution process in a star-connection architecture, in order to guarantee the same transmission line lengths and therefore a good clock alignment between the components, devices, circuits. The star-connection architecture is also required for the LO signal to achieve phase coherence when all the TRx channels are used as one antenna array. The requirement to adopt a star-connection architecture for all common signals (LO signal, MS clock, etc.) imposes severe constraints on the PCB design. A common and synchronised phase reference is particularly important in a distributed radar phased array design, in order to steer a beam and control a radiation pattern for the phased array system.
Synchronised clock signals are also used to sample data inside the ADCs of each device. In an FMCW radar device, the synchronized clock edges are used to sample data and control signals that are used to start the modulation. Here, the RFS signal across all devices must be synchronized. This alignment is needed to avoid sampling valid data at different times/moments in the master and slave devices, which would create phase errors between devices and consequently compromise radar system performance.
Even when adopting a star-connection architecture, a problem occurs when the RFS signal edge is close to a MS clock edge. Particularly in response to processing, voltage or temperature (PVT) variations, a master device and one or more slave device(s) may observe RFS re-timed at a different clock edges. This means that for an intermediate frequency (IF) of, say, IF=20 MHz, an error of a complete 240 MHz MS clock cycle can happen. This leads to a phase error of around +/−15 degrees, which compromises radar angular resolution. Modern imaging radar systems specifications allow a maximum of +/−3 degrees of phase error, and this considers errors due to combined ADC sampling and receiver channel variations, as well as some PCB asymmetries. This translates to a stringent required synchronization time accuracy of around 416 psec., for a maximum intermediate frequency (IF) of 20 MHz.
LVDS is a technical standard that specifies electrical characteristics of a differential, serial communications protocol. LVDS operates at low power with programmable output amplitude of voltages and can run at very high speeds using inexpensive twisted-pair copper cables. FIG. 2 illustrates a known, classical LVDS communication link 200, that includes an LVDS transmitter 205 The LVDS transmitter 205 (or driver) provides a constant output current (e.g. 3.5 mA) generally terminated by a 100 ohm accurate external differential load termination 215. The LVDS transmitted signal 220 is a differential signal that is received by the LVDS receiver 210 and converted in general to a single ended CMOS output 225 that is used as a clock within circuits inside the LVDS receiver 210.
FIG. 3 illustrates a more detailed circuit diagram of the conventional LVDS transmitter 205 of FIG. 2. The LVDS transmitter 205 (or driver) provides a constant output current (e.g. 3.5 mA) generally terminated by a 100 ohm accurate external differential load termination 215. The conventional LVDS transmitter 205 employs a regulation loop 310 that outputs differential voltages (positive and negative bias voltages 315, 325) and a common mode voltage 320 to a switched LVDS circuit 330. In such a conventional LVDS transmitter 205, there is no specific attention made on timing constraints (e.g. settling time) of the circuit, or in a master-slave device architecture, no consideration of synchronization when switching amplitude levels. Indeed, the output of the conventional LVDS transmitter 205 only changes by directly changing the output current itself, and this change takes some time to recover from current overshooting, due to the intrinsic output common mode loop reaction time. This limitation does not support fast transitions and presents too much delay variation. Consequently, such architectures, in their present form, cannot be used in cascaded radar systems.
U.S. Pat. No. 6,775,328 B1 proposes a feedback synchronization loop using mV input-output drivers and receivers, U.S. Pat. No. 9,031,180 B2 provides synchronization via a protocol (data frame) in wireless transmitters, U.S. Pat. No. 7,876,261 B1 proposes synchronization between devices using reflected wave clock synchronization. U.S. Pat. No. 6,209,072 B1 uses a de-skewing latch technique in order to obtain a synchronous interface between master device and slave devices. Each of these known techniques is complex and/or require further components and circuits, thereby requiring valuable PCB space and increased cost.
Thus, a mechanism is needed to better support synchronization between shared clocks signals (that use a master-slave clock) and a ramp frame start (RFS) signal in radar units that use multiple radar devices or ICs.